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HT1660 9632 LCD Controller for I/O MCU
Features
* Operating voltage: 2.7V~5.2V * Built-in 32kHz RC oscillator * External 32.768kHz crystal oscillator or 32kHz fre* Six-wire interface (four data wires) * Eight kinds of time base/WDT selection * Time base or WDT overflow output * R/W address auto increment * Built-in buzzer driver (2kHz/4kHz) * Power down command reduces power consumption * Software configuration feature * Data mode and Command mode instructions * Three data accessing modes * Provides VLCD pin to adjust LCD operating voltage
quency source input
* Standby current: <1mA at 3V, <2mA at 5V * Internal resistor type: 1/6 bias or 1/5 bias, 1/32 duty,
or 1/16 duty
* Three selectable LCD frame frequencies: 64Hz,
89Hz or 170Hz
* Max. 9632 patterns, 96 segments and 32 commons * 112 segments and 16 commons selectable by com-
and max. VLCD voltage up to 7V
* Provides three kinds of bias current programming * Control of TN-type and STN-type LCDs * 160-pin QFP package
mand method
* Built-in bit-map display RAM: 3072 bits (=9632 bits) * Built-in internal resistor type bias generator
Applications
* Leisure products * Games * Personal digital assistant * Cellular phone * Global positioning system * Consumer electronics
General Description
HT1660 is a peripheral device specially designed for I/O type MCU used to expand the display capability. The max. display segment of the device are 3072 patterns (96 segments and 32 commons). It also supports four data bits interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1660 is a memory mapping and multi-function LCD controller. Since the HT1660 can control TN-type (Twisted Nematic) or STN-type (Super Twisted Nematic) LCDs. The software configuration feature of the HT1660 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only six lines (CS, WR, DB0~DB3) are required for the interface between the host controller and the HT1660.
Rev. 1.00
1
September 16, 2003
HT1660
Block Diagram
OSCO OSCI CS RD WR DB0 DB3 VDD VSS BZ BZ T o n e F re q u e n c y G e n e ra to r W a tc h d o g T im e r & T im e B a s e G e n e r a to r SEG 95 VLCD IR Q C o n tro l & T im in g C ir c u it D is p la y R A M
COM0 L C D D r iv e r / B ia s C ir c u it CO M 31 SEG0
N o te : C S : C h ip s BZ,BZ:To W R,RD:W D B0~D B3: CO M 0~CO IR Q : T im e
e le c tio n n e o u tp u ts R IT E c lo c k , R E A D c lo c k D a ta b u s M 3 1 , S E G 0 ~ S E G 9 5 : L C D o u tp u ts b a s e o r W D T o v e r flo w o u tp u t
Pin Assignment
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM COM COM COM COM COM COM COM COM 22 23 24 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 20 21
CO CO CO CO
M 19 M 18 M 17 M 16 NC NC NC NC NC NC CS RD WR DB0 DB1 DB2 DB3 VSS OSCI OSCO VDD VLCD IR Q BZ BZ T1 T2 T3 T4 T000 VLCD NC NC NC NC NC COM0 COM1 COM2 COM3
16015915815715615515415315215115014914814714614514414314214114013913813713613513413313213113012912812712612512412312212 1 1 1 1 1 1 1 1 1 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 H T1660 1 1 1 6 0 Q F P -A
1 20
19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE
G6 G6 G6 G6 G6 G6 G6 G6 G5 G5 G5 G5 G5 G5 G5 G5 G5 G5 G4 G4 G4 G4 G4 G4 G4 G4 G4 G4 G3 G3 G3 G3 G3 G3 G3 G3 G3 G3 G2 G2 8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM COM COM COM COM COM COM COM COM 0 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 4 5 6 7 8 9 10 11
Rev. 1.00
2
September 16, 2003
HT1660
Pad Assignment
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 51 52 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 62
149
61
148
60
147 146
59
58
145
57
144 143
56
55
142
54
141
53
140
139
138
137
136
135
134
133
132 131
130
129 128
127 126 125
124
123 122
121 120 119
118 117 116 115 114
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM COM COM COM COM COM COM COM COM COM
63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 31 30 29 28 27 26 25 24 23 22 21 20 19 3 4 5 6 7 8 9 2
1
113 112 111 110 109 108 107 106 105 104 103 102 101 100
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
99 98 97 (0 ,0 ) 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 50 47 48 49 WR DB1 DB2 DB3 VSS OSCI OSCO CS RD DB0 CO M 16 CO M 17 CO M 18 51 52 53 54 55 56 57 58 59 61 60 VLCD VDD IR Q 62 63 64 65 66 67 68 69 70 71 72 73 COM2 COM1 COM0 BZ BZ T1 T2 T3 T4 VLCD T000
SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE CO CO CO CO CO CO CO CO CO CO CO CO CO
G3 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 G1 G1 G1 G1 G1 G1 G1 G1 G1 G1 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 M1 M1 M1 M1 M1 M1 M9 M8 M7 M6 M5 M4 M3
0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0
Chip size: 43405030 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.00
3
September 16, 2003
HT1660
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 X -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50V -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -2028.50 -1523.55 -1423.55 -1323.55 -1170.45 Y 2237.20 2137.20 2037.20 1937.20 1837.20 1637.20 1537.20 1437.20 1337.20 1237.20 1237.20 1137.20 1037.20 937.20 837.20 737.20 637.20 537.20 437.20 337.20 237.20 137.20 37.20 -62.80 -162.80 -262.80 -362.80 -462.80 -562.80 -662.80 -762.80 -862.80 -962.80 -1062.80 -1162.80 -1262.80 -1362.80 -1462.80 -1562.80 -1662.80 -1762.80 -1862.80 -1962.80 -2062.80 -2162.80 -2262.80 -2337.10 -2337.10 -2337.10 -2225.20 Pad No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 X -1027.85 -892.45 -745.55 -610.15 -464.85 -329.25 -187.15 -53.65 84.55 222.85 310.40 492.00 638.50 773.90 933.50 1081.70 1228.70 1376.90 1523.90 1662.50 1821.19 1921.19 2021.19 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 Y -2225.20 -2225.20 -2225.20 -2225.20 -2225.20 -2225.20 -2225.30 -2229.70 -2229.70 -2297.35 -2162.35 -2183.60 -2225.30 -2225.30 -2225.30 -2225.30 -2225.30 -2225.30 -2225.30 -2225.30 -2338.90 -2338.90 -2338.90 -2051.10 -1951.10 -1851.10 -1751.10 -1651.10 -1551.10 -1451.10 -1351.10 -1251.10 -1151.10 -1051.10 -951.10 -851.10 -745.80 -645.80 -545.80 -445.80 -345.80 -245.80 -145.80 -45.80 54.20 154.20 254.20 354.20 454.20 554.20 Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 X 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 2028.45 1550.75 1450.75 1350.75 1250.75 1150.75 1050.75 950.75 850.75 750.75 650.75 550.75 450.75 350.75 250.75 150.75 50.75 -49.25 -149.25 -249.25 -349.25 -449.25 -549.25 -649.25 -749.25 -849.25 -949.25 -1049.25 -1149.25 -1249.25 -1349.25 -1449.25 -1549.25 Unit: mm Y 654.20 754.20 854.20 954.20 1054.20 1154.20 1254.20 1354.20 1454.20 1554.20 1654.20 1754.20 1854.20 1954.20 2054.20 2154.20 2254.20 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60 2349.60
Rev. 1.00
4
September 16, 2003
HT1660
Pad Description
Pad No. 1~33 87~149 34~49 71~86 Pad Name SEG63~SEG95 SEG0~SEG62 COM31~COM16 COM0~COM15 I/O O LCD segment outputs LCD common outputs, under 11216 command mode, COM16~COM31 will share to SEG96~SEG111. COM31/SEG96, COM30/SEG97, COM29/ SEG98....., COM18/SEG109, COM17/SEG110, COM16/SEG111 Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or write to the HT1660 are disabled. The serial interface circuit is also reset. But if the CS is at a logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1660 are all enabled. READ clock input with pull-high resistor. Data in the RAM of the HT1660 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next rising edge to latch the clocked out data. WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT1660 on the rising edge of the WR signal. Parallel data input/output with a pull-high resistor Negative power supply for logic circuit, ground The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected, the OSCI and OSCO pads can be left open. Positive power supply for logic circuit Power supply for LCD driver circuit Time base or Watchdog Timer overflow flag, NMOS open drain output. 2kHz or 4kHz frequency output pair (tristate output buffer) Not connected Description
O
50
CS
I
51
RD
I
52 53~56 57
WR DB0~DB3 VSS
I I/O 3/4
58 59
OSCI OSCO
I O
60 61 62 63, 64 65~69
VDD VLCD IRQ BZ, BZ T1~T4, T000
3/4 I O O I
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+5.5V Input Voltage.............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
5
September 16, 2003
HT1660
D.C. Characteristics
Symbol VDD IDD1 IDD2 IDD11 IDD22 ISTB VIL VIH IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 RPH Parameter Operating Voltage Operating Current Test Conditions VDD 3/4 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V Conditions 3/4 No load/LCD ON On-chip RC oscillator No load/LCD ON Crystal oscillator No load/LCD OFF On-chip RC oscillator No load/LCD OFF Crystal oscillator No load, Power down mode Min. 2.7 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0 2.4 4.0 1.2 3 -1.8 -2 1.2 3 -1.8 -4 80 180 -80 -180 50 120 -60 -140 150 60 Typ. 3/4 150 250 135 200 15 50 2 3 3/4 3/4 3/4 3/4 3/4 3/4 2.5 6 -0.9 -4 2.5 6 -0.9 -2 160 360 -40 -90 100 240 -30 -70 250 125 Max. 5.2 250 370 200 300 30 70 10 10 1 2 0.6 1.0 3 5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 350 180 Ta=25C Unit V mA mA mA mA mA mA mA mA mA mA V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA kW kW
Operating Current
Operating Current
Operating Current
Standby Current
Input Low Voltage
DB0~DB3, WR, CS, RD
Input High Voltage
DB0~DB3, WR, CS, RD VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V DB0~DB3, WR, CS, RD
BZ, BZ, IRQ Sink Current
BZ, BZ Source Current
DB0~DB3 Sink Current
DB0~DB3 Source Current
LCD Common Sink Current
LCD Common Source Current
LCD Segment Sink Current
LCD Segment Source Current
Pull-high Resistor
Rev. 1.00
6
September 16, 2003
HT1660
A.C. Characteristics
Symbol Parameter Test Conditions VDD 3V System Clock 5V 3V fSYS2 System Clock 5V 3V fSYS3 System Clock 5V fLCD1 3V LCD Frame Frequency 5V 3V fLCD2 LCD Frame Frequency 5V 3V fLCD3 tCOM fCLK1 LCD Frame Frequency 5V LCD Common Period 4-Bit Data Clock (WR Pin) 5V 3V fCLK2 4-Bit Data Clock (RD Pin) 5V tCS 4-Bit Interface Reset Pulse Width (Figure 3) 3/4 3V tCLK Read mode WR, RD Input Pulse Width (Figure 1) Write mode 5V Read mode tr, tf Rise/Fall Time Serial Data Clock 3V Width (Figure 1) 5V Setup Time for DB to WR, RD Clock 3V Width (Figure 2) 5V Hold Time for DB to WR, RD Clock 3V Width (Figure 2) 5V Setup Time for CS to WR, RD Clock 3V Width (Figure 3) 5V Hold Time for CS to WR, RD Clock 3V Width (Figure 3) 5V 3/4 3.34 3/4 1.67 3/4 3/4 ms 6.67 CS Write mode Duty cycle 50% 3/4 3V Duty cycle 50% n: Number of COM External clock source Crystal oscillator On-chip RC oscillator 61/117 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3.34 89/170 111/213 64 64 64 64 n/fLCD 3/4 3/4 3/4 3/4 250 3/4 3/4 3/4 3/4 3/4 3/4 150 300 75 150 3/4 3/4 Hz Hz Hz Hz Hz sec kHz kHz kHz kHz ns ms External clock source Crystal oscillator On-chip RC oscillator 24 3/4 3/4 3/4 3/4 61/117 32 32.768 32.768 32 32 40 3/4 3/4 3/4 3/4 kHz kHz kHz kHz kHz Hz Conditions Min. 22 Typ. 32 Max. 40 Ta=25C Unit kHz
fSYS1
89/170 111/213
120
3/4
ns
tsu
3/4
3/4
120
3/4
ns
th
3/4
3/4
120
3/4
ns
tsu1
3/4
3/4
100
3/4
ns
th1
3/4
3/4
100
3/4
ns
Rev. 1.00
7
September 16, 2003
HT1660
V a lid D a ta DB 50% ts
u
V th
DD
tf W R,RD C lo c k 90% 50% 10%
tr
V
DD
GND
tC
LK
tC
GND
LK
W R,RD C lo c k
50%
GND
Figure 1
tC
S
Figure 2
CS
50% ts
u1
V
DD
th
1
GND V
DD
W R,RD C lo c k
50% F ir s t C lo c k Last C lo c k
GND
Figure 3
Functional Description
System Oscillator The HT1660 system clock is used to generate the time base/Watchdog Timer (WDT) clock frequency, LCD driving clock, and tone frequency. The clock source may be from an on-chip RC oscillator (32kHz), a crystal oscillator (32.768kHz), or an external 32kHz clock by the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias generator will turn off. That command is available only for the on-chip RC oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and the time base/WDT loses its function as well.
OSCI OSCO C r y s ta l O s c illa to r 32768H z E x te r n a l C lo c k S o u r c e 32kH z O n - c h ip R C O s c illa to r 32kH z
The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, thus serving as a system power down command. But if the external clock source is chosen as the system clock, using the SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal oscillator option can be applied to connect an external frequency source of 32kHz to the OSCI pin. In this case, the system fails to enter the power down mode, similar to the case in the external 32kHz clock source operation. At the initial system power on, the HT1660 is at the SYS DIS state.
S y s te m C lo c k
System Oscillator Configuration
Rev. 1.00
8
September 16, 2003
HT1660
Display Memory - RAM Structure The static display RAM is organized into 7684 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns. 00H COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 Bit0 Bit1 Bit2 Bit3 01H Bit0 Bit1 Bit2 Bit3 02H Bit0 Bit1 Bit2 Bit3 03H Bit0 Bit1 Bit2 Bit3 04H Bit0 Bit1 Bit2 Bit3 05H Bit0 Bit1 Bit2 Bit3 06H Bit0 Bit1 Bit2 Bit3 07H Bit0 Bit1 Bit2 Bit3 SEG0 08H Bit0 Bit1 Bit2 Bit3 09H Bit0 Bit1 Bit2 Bit3 0AH Bit0 Bit1 Bit2 Bit3 0BH Bit0 Bit1 Bit2 Bit3 0CH Bit0 Bit1 Bit2 Bit3 0DH Bit0 Bit1 Bit2 Bit3 0EH Bit0 Bit1 Bit2 Bit3 0FH Bit0 Bit1 Bit2 Bit3 SEG1 10H Bit0 Bit1 Bit2 Bit3 11H Bit0 Bit1 Bit2 Bit3 12H Bit0 Bit1 Bit2 Bit03 13H Bit0 Bit1 Bit2 Bit3 14H Bit0 Bit1 Bit2 Bit3 15H Bit0 Bit1 Bit2 Bit3 16H Bit0 Bit1 Bit2 Bit3 17H Bit0 Bit1 Bit2 Bit3 SEG2 SEG3 SEG92 1FH 27H - - - - - - - - - 2DFH 2E7H 1EH 26H- - - - - - - - - 2DEH 2E6H 1DH 25H- - - - - - - - - 2DDH 2E5H 1CH 24H- - - - - - - - - 2DCH 2E4H 1BH 23H- - - - - - - - - 2DBH 2E3H 1AH 22H- - - - - - - - - 2DAH 2E2H 19H 21H - - - - - - - - - 2D9H 2E1H 18H 20H - - - - - - - - - 2D8H 2E0H 2E8H Bit0 Bit1 Bit2 Bit3 2E9H Bit0 Bit1 Bit2 Bit3 2EAH Bit0 Bit1 Bit2 Bit3 2EBH Bit0 Bit1 Bit2 Bit3 2ECH Bit0 Bit1 Bit2 Bit3 2EDH Bit0 Bit1 Bit2 Bit3 2EEH Bit0 Bit1 Bit2 Bit3 2EFH Bit0 Bit1 Bit2 Bit3 SEG93 2F0H Bit0 Bit1 Bit2 Bit3 2F1H Bit0 Bit1 Bit2 Bit3 2F2H Bit0 Bit1 Bit2 Bit3 2F3H Bit0 Bit1 Bit2 Bit3 2F4H Bit0 Bit1 Bit2 Bit3 2F5H Bit0 Bit1 Bit2 Bit3 2F6H Bit0 Bit1 Bit2 Bit3 2F7H Bit0 Bit1 Bit2 Bit3 SEG94 2F8H Bit0 Bit1 Bit2 Bit3 2F9H Bit0 Bit1 Bit2 Bit3 2FAH Bit0 Bit1 Bit2 Bit3 2FBH Bit0 Bit1 Bit2 Bit3 2FCH Bit0 Bit1 Bit2 Bit3 2FDH Bit0 Bit1 Bit2 Bit3 2FEH Bit0 Bit1 Bit2 Bit3 2FFH Bit0 Bit1 Bit2 Bit3 SEG95
9632 Selection Mode RAM Mapping Table
Rev. 1.00
9
September 16, 2003
HT1660
00H COM0 COM1 COM2 COM3 Bit0 Bit1 Bit2 Bit3 01H COM4 COM5 COM6 COM7 Bit0 Bit1 Bit2 Bit3 02H COM8 COM9 COM10 COM11 Bit0 Bit1 Bit2 Bit3 03H COM12 COM13 COM14 COM15 Bit0 Bit1 Bit2 Bit3 SEG0 04H Bit0 Bit1 Bit2 Bit3 05H Bit0 Bit1 Bit2 Bit3 06H Bit0 Bit1 Bit2 Bit3 07H Bit0 Bit1 Bit2 Bit3 SEG1 08H Bit0 Bit1 Bit2 Bit3 09H Bit0 Bit1 Bit2 Bit3 0AH Bit0 Bit1 Bit2 Bit3s 0BH Bit0 Bit1 Bit2 Bit3 SEG2 SEG3 0FH 13H - - - - - - - - - 1AFH 1B3H 0EH 12H- - - - - - - - - 1AEH 1B2H 0DH 11H- - - - - - - - - 1ADH 1B1H 0CH 10H- - - - - - - - - 1ACH 1B0H 1B4H Bit0 Bit1 Bit2 Bit3 1B5H Bit0 Bit1 Bit2 Bit3 1B6H Bit0 Bit1 Bit2 Bit3 1B7H Bit0 Bit1 Bit2 Bit3 1B8H Bit0 Bit1 Bit2 Bit3 1B9H Bit0 Bit1 Bit2 Bit3 1BAH Bit0 Bit1 Bit2 Bit3 1BBH Bit0 Bit1 Bit2 Bit3 1BCH Bit0 Bit1 Bit2 Bit3 1BDH Bit0 Bit1 Bit2 Bit3 1BEH Bit0 Bit1 Bit2 Bit3 1BFH Bit0 Bit1 Bit2 Bit3
SEG108 SEG109 SEG110 SEG111
11216 Selection Mode RAM Mapping Table Name 11216 Mode Command Code X100-0001-1111-XXXX Function Change segment from 96 to 112 and common from 32 to 16
The default value after power ON reset is 9632 mode, set Normal command will change 11216 mode to 9632 mode. Frame Frequency HT1660 provides three kinds of frame frequency option by command code; 64Hz, 89Hz and 170Hz respectively. FRAME 64Hz provides 64Hz frame frequency. FRAME 89Hz provides 89Hz frame frequency. FRAME 170Hz provides 170Hz frame frequency. Name FRAME 170Hz FRAME 89Hz FRAME 64Hz Command Code X100-0001-1000-XXXX X100-0001-1101-XXXX X100-0001-1110-XXXX Function Select 170Hz frame frequency Select 89Hz frame frequency Select 64Hz frame frequency
Frame Frequency Selection Command Code Time Base and Watchdog Timer - WDT The time base generator and WDT share the same counter which is divided by 256. The IRQ clock can be programmed as 1Hz, 2Hz, ...., 128Hz output. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will remain at a logic low level until the CLR WDT or the IRQ DIS command is issued. If an external clock is selected as the system frequency source, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed.
Rev. 1.00
10
September 16, 2003
HT1660
Buzzer Tone Output A simple tone generator is implemented in the HT1660. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. By executing the TONE 4K and TONE 2K commands there are two tone frequency outputs selectable that can turn on the tone output. The TONE 4K and TONE 2K commands set the tone frequency to 4kHz and 2kHz, respectively. The tone output can be turned off by invoking the TONE OFF command. The tone outputs, namely BZ and BZ, are a pair of differential driving outputs used to drive a piezo buzzer. Once the system is disabled or the tone output is inhibited, the BZ and the BZ outputs will remain at low level. Command Format The HT1660 can be configured by software setting. There are two mode commands to configure the HT1660 resource and to transfer the LCD display data. The configuration mode of the HT1660 is called command mode, and its command mode ID is 100. The command mode consists of a system configuration
T im e B a s e C lo c k S o u r c e 256 V CLR T im e r
DD
command, a system frequency selection command, an LCD configuration command, a tone frequency selection command, a bias current selection command, a timer/WDT setting command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. The following are the data mode ID and the command mode ID: Operation READ WRITE READ-MODIFY-WRITE COMMAND Mode Data Data Data Command ID 110 101 101 100
If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to 1 and the previous operation mode will also be reset. The CS pin returns to 0, so a new operation mode ID should be issued first.
T IM E R E N /D IS W D T E N /D IS D CK R Q IR Q E N /D IS
IR Q
W DT 4
CLR
W DT
Time Base and WDT Configurations
Name TONE OFF TONE 4K TONE 2K
Command Code X100-0000-1000-XXXX X100-0001-0000-XXXX X100-0001-0001-XXXX Turn-off tone output
Function
Turn-on tone output, tone frequency is 4kHz Turn-on tone output, tone frequency is 2kHz
Buzzer Tone Output Command Code The following are the data mode ID and the command ID: Operation READ WRITE READ-MODIFY-WRITE COMMAND Mode Data Data Data Command ID 110 101 101 100
If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive address data mode, the CS pin should be set 1 and the previous operation mode will also be reset. The CS pin returns to 0, so a new operation mode ID should be issued first.
Rev. 1.00
11
September 16, 2003
HT1660
Bias Generator The HT1660 bias voltage belongs to internal resistor type. It provides two kinds of bias option named 1/6 bias and 1/5 bias respectively. It also provides three kinds of bias current option by programming to suitably drive an LCD panel. The three kinds of bias current are large, middle, and small, respectively. Usually, large panel LCD can be excellently displayed by large bias current. Relatively, it consumes large current when LCD ON command is used. Small bias current provides low power consumption during on condition when the LCD is normally displayed. The following are the reference value table. Interfacing Only six lines are required to interface with the HT1660. The CS line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the HT1660. If the CS pin is set to 1, the data and command issued between the host controller and the HT1660 are first disabled and then initialized. Bias 1/5 5V 3V 1/6 5V 225mA 90mA 40mA 270mA 140mA 110mA 55mA 50mA 25mA VLCD 3V Large Bias Current 165mA Before issuing a mode command or mode switching, a high level pulse is required to initialize the serial interface of the HT1660. The DB0~DB3 are the 4-bit parallel data input/output lines. Data to be read or written or commands to be written have to pass through the DB0~DB3 lines. The RD line is the READ clock input. Data in the RAM are clocked out on the falling edge of the RD signal, and the clocked out data will then appear on the DB0~DB3 lines. It is recommended that the host controller read correct data during the interval between the rising edge and the next falling edge of the RD signal. The WR line is the WRITE clock input. The data, address, and command on the DB0~DB3 lines are all clocked into the HT1660 on the rising edge of the WR signal. There is an optional IRQ line to be used as an interface between the host controller and the HT1660. The IRQ pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT function by connecting with the IRQ pin of the HT1660.
Middle Bias Current 70mA
Small Bias Current 30mA
Power VLCD R V1 R V2 R V3 R V4 R V5 R V6 R VSS 1 /6 B ia s N o te : T h e v o lta g e a p p lie d to V L C D A d ju s t V R to fit L C D d is p la y V
LCD
Power VR VLCD R V1 R V2 R V3 R V4 R V5 R V6 R VSS 1 /5 B ia s p in m u s t b e lo w e r th a n 7 V V
LCD
VR
Internal Resistor Type Bias Generator Configurations
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September 16, 2003
HT1660
D a ta (M A + 1 5 ) D3 D a ta (M A + 1 4 ) D3 D a ta (M A + 1 3 ) D a ta (M A + 1 2 ) D a ta (M A + 1 1 ) D a ta (M A + 1 0 ) ( S u c c e s s iv e a d d r e s s r e a d in g ) D a ta (M A + 9 ) D a ta (M A + 8 ) D a ta (M A + 7 ) D a ta (M A + 6 ) D a ta (M A + 5 ) D a ta (M A + 4 ) D a ta (M A + 3 ) D a ta (M A + 2 ) D a ta (M A + 1 ) D a ta (M A ) M e m o ry A d d re s s (M A ) A d d re s s (M A ) C o m m a n d ID code D3
D a ta (M A + 1 5 ) D2 D1 D0 D a ta (M A + 1 4 ) D2 D1 D0 D a ta (M A + 1 3 ) D2 D1 D0 D a ta (M A + 1 2 )
D a ta (M A + 1 1 ) D3 D2 D1 D0 D a ta (M A + 1 0 ) D3 D2 D1 D0 D a ta (M A + 9 ) D3 D2 D1 D0 D a ta (M A + 8 ) D3 D2 D1 D0 D a ta (M A + 7 ) D3 D2 D1 D0 D a ta (M A + 6 ) D3 D2 D1 D0 D a ta (M A + 5 ) D3 D2 D1 D0 D a ta (M A + 4 ) D3 D2 D1 D0 D a ta (M A + 3 ) D3 D2 D1 D0 D a ta (M A + 2 ) D3 D2 D1 D0 D a ta (M A + 1 ) D3 D2 D1 D0 D a ta (M A ) D3 D2 D1 D0 A3 A1 A2 A0 M e m o ry A d d re s s (M A ) A7 A5 A6 A4 A d d re s s (M A ) A9 A8 X X C o m m a n d ID 1 code X 1 0
D3
D2
D1
D3
D2
D1
D0
D0
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D0
D0
D0
D0
( S u c c e s s iv e a d d r e s s r e a d in g )
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D0
D0
D0
D0
D0
D0
A3
A1
A7
A2
A5
A6
A9
1
X
1
0
A8
X
X
A4
A0
( S in g le a d d r e s s r e a d in g )
Timing Diagrams
M e m o ry A3 A2 A1 A0 A d d re s s (M A ) A7 A6 A5 A4 A d d re s s (M A ) A9 A8 X X C o m m a n d ID 1 1 0 X code
M e m o ry A3 A2 A1 A0 A d d re s s (M A ) A7 A6 A5 A4 A d d re s s (M A ) A9 A8 X X C o m m a n d ID 1 1 X 0 code
( S in g le a d d r e s s r e a d in g )
D a ta (M A ) D2 D1 D0
WRITE Mode (Command ID Code: 1 0 1)
READ Mode (Command ID Code: 1 1 0)
D a ta (M A ) D3 D2 D1 D0
D3
Rev. 1.00
WR DB3 DB2 DB1 DB0 WR DB3 DB2 DB1 DB0 RD CS RD
CS
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September 16, 2003
D3 D2 D1 D0
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D0
D0
D0
D0
HT1660
READ-MODIFY-WRITE Mode (Command ID Code: 1 0 1)
CS
WR
RD
DB3
X
X
A7
A3
D3
D3 X
X
A7
A3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
DB2
1 X
A6
A2
D2
D2 1
X
A6
A2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
DB1
1
A9
A5
A1
D1
D1 1
A9
A5
A1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
DB0
0 C o m m a n d ID code
A8 A d d re s s (M A )
A4 A d d re s s (M A )
A0 M e m o ry
D0 D a ta (M A )
D0
0 C o m m a n d ID code
A8 A d d re s s (M A )
A4 A d d re s s (M A )
A0 M e m o ry
D0 D a ta (M A )
D0 D a ta (M A )
D0 D a ta (M A + 1 )
D0 D a ta (M A + 1 )
D0 D a ta (M A + 2 )
D0 D a ta (M A + 2 )
D0 D a ta (M A + 3 )
D0 D a ta (M A + 3 )
D0 D a ta (M A + 4 )
D0 D a ta (M A + 4 )
D0 D a ta (M A + 5 )
D0 D a ta (M A + 5 )
D0 D a ta (M A + 6 )
D0 D a ta (M A + 6 )
D0 D a ta (M A + 7 )
D0 D a ta (M A + 7 )
( S in g le a d d r e s s r e a d in g )
( S u c c e s s iv e a d d r e s s r e a d in g )
Command Mode (Command ID Code: 1 0 0)
CS
WR
RD
DB3
X
C7
C3
X
X X
C7
C3
X
X
C7
C3
X
X
C7
C3
X
X
C7
C3
X
X
C7
C3
DB2
1
C6
C2
X
X
1
C6
C2
X
X
C6
C2
X
X
C6
C2
X
X
C6
C2
X
X
C6
C2
DB1
0
C5
C1
X X
0
C5
C1
X
X
C5
C1
X
X
C5
C1
X
X
C5
C1
X
X
C5
C1
DB0
0 C o m m a n d ID code
C4
C0 Com m and
X X
0 C o m m a n d ID c o d e
C4
C0 C om m and 1
X
X
C4
C0 C om m and 2
X
X
C4
C0
X C om m and 3
X
C4
C0
X C om m and 4
X
C4
C0 C om m and 5
( S in g le c o m m a n d )
( S u c c e s s iv e c o m m a n d )
Note: X stands for dont care
Rev. 1.00
14
September 16, 2003
HT1660
Application Circuits
Host Controller With an HT1660 Display System
M ax. 7V
*
MCU
*R
CS RD WR D B0~D B3
*V R
H T1660
VLCD BZ P ie z o BZ
IR Q OSCI C lo c k O u t E x te r n a l C lo c k 1 ( 3 2 k H z ) E x te r n a l C lo c k 2 ( 3 2 k H z ) O n - c h ip O S C * 1 /6 B ia s o r 1 /5 B ia s , 1 /3 2 D u ty o r 1 /1 6 D u ty OSCO C O M 0 ~ C O M 31 SEG 0~SEG 95
LCD
C ry s ta l 32768H z
Panel
Note:
* The connection of IRQ and RD pin can be selected depending on the MCU. Adjust VR to fit LCD display Adjust R (external pull-high resistance) to fit users time base clock.
Instruction Set Summary
Name READ WRITE Command Code X110-XXA9A8-A7A6A5A4-A3A2A1A0D3D2D1D0 X101-XXA9A8-A7A6A5A4-A3A2A1A0D3D2D1D0 D/C D D D C C C C C C C C C C C C Function Read data from the RAM Write data to the RAM Read and Write data to the RAM Turn Off both system oscillator and LCD bias Yes generator Turn On system oscillator Turn Off LCD display Turn On LCD display Disable time base output Disable WDT time-out flag output Enable time base output Enable WDT time-out flag output Turn Off tone outputs Clear the contents of the time base generator Clear the contents of the WDT stage Turn on tone output, tone frequency output: 4kHz Yes Yes Yes Yes Def.
READ-MODIFY- X101-XXA9A8-A7A6A5A4-A3A2A1A0WRITE D3D2D1D0 SYS DIS SYS EN LCD OFF LCD ON TIMER DIS WDT DIS TIMER EN WDT EN TONE OFF CLR TIMER CLR WDT TONE 4K X100-0000-0000-XXXX-XXXX X100-0000-0001-XXXX-XXXX X100-0000-0010-XXXX-XXXX X100-0000-0011-XXXX-XXXX X100-0000-0100-XXXX-XXXX X100-0000-0101-XXXX-XXXX X100-0000-0110-XXXX-XXXX X100-0000-0111-XXXX-XXXX X100-0000-1000-XXXX-XXXX X100-0000-1101-XXXX-XXXX X100-0000-1111-XXXX-XXXX X100-0001-0000-XXXX-XXXX
Rev. 1.00
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HT1660
Name TONE 2K IRQ DIS IRQ EN RC 32K EXT (XTAL) LARGE BIAS MIDDLE BIAS SMALL BIAS BIAS 1/6 BIAS 1/5 FRAME 170Hz FRAME 89Hz FRAME 64Hz Select 11216 F1 F2 F4 F8 F16 F32 F64 F128 TEST NORMAL Note: Command Code X100-0001-0001-XXXX-XXXX X100-0001-0010-XXXX-XXXX X100-0001-0011-XXXX-XXXX X100-0001-0100-XXXX-XXXX X100-0001-0101-XXXX-XXXX X100-0001-0110-XXXX-XXXX X100-0001-0111-XXXX-XXXX X100-0001-1000-XXXX-XXXX X100-0001-1010-XXXX-XXXX X100-0001-1001-XXXX-XXXX X100-0001-1100-XXXX-XXXX X100-0001-1101-XXXX-XXXX X100-0001-1110-XXXX-XXXX X100-0001-1111-XXXX-XXXX X100-1010-0000-XXXX-XXXX X100-1010-0001-XXXX-XXXX X100-1010-0010-XXXX-XXXX X100-1010-0011-XXXX-XXXX X100-1010-0100-XXXX-XXXX X100-1010-0101-XXXX-XXXX X100-1010-0110-XXXX-XXXX X100-1010-0111-XXXX-XXXX X100-1111-1111-XXXX-XXXX X100-1111-1110-XXXX-XXXX D/C C C C C C C C C C C C C C C C C C C C C C C C C Function Turn on tone output, tone frequency output: 2kHz Disable IRQ output Enable IRQ output System clock source, on-chip RC oscillator System clock source, external 32kHz clock source or crystal oscillator 32.768kHz Large bias current option Middle bias current option Small bias current option LCD 1/6 bias option LCD 1/5 bias option Selects 170Hz frame frequency Selects 89Hz frame frequency Selects 64Hz frame frequency This command will change segment from 96 to 112 and command from 32 to 16 Time base clock output: 1Hz The WDT time-out flag after: 4s Time base clock output: 2Hz The WDT time-out flag after: 2s Time base clock output: 4Hz The WDT time-out flag after: 1s Time base clock output: 8Hz The WDT time-out flag after: 1/2s Time base clock output: 16Hz The WDT time-out flag after: 1/4s Time base clock output: 32Hz The WDT time-out flag after: 1/8s Time base clock output: 96Hz The time-out flag after: 1/16s Time base clock output: 128Hz The WDT time-out flag after: 1/32s Test mode, user dont use. Normal mode, 9632 mode will be set Yes Yes Yes Yes Yes Yes Yes Def.
X stands for dont care A9~A0: RAM address D3~D0: RAM data D/C: Data/Command mode Def.: Power-on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The tone frequency source and the time base/WDT clock frequency source can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1660 after power-on reset, otherwise, power on reset may fail, which in turn leads to the malfunctioning of the HT1660.
Rev. 1.00
16
September 16, 2003
HT1660
Package Information
160-pin QFP (2828) Outline Dimensions
C D 120 81 G H
I 121 80
A
B F
E
160
41 K 1 40 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 31 27.90 31 27.90 3/4 3/4 3.10 3/4 3/4 0.65 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 31.40 28.10 31.40 28.10 3/4 3/4 3.40 3.70 3/4 0.95 0.20 7
Rev. 1.00
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September 16, 2003
HT1660
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2003 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
18
September 16, 2003

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